Apparatus and method for operating a dual port memory cell
US6252818A · kind A · utility
10Cited by
3References
8Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 26, 1999 |
| Grant date | Jun 26, 2001 |
| Priority date | — |
| Expiry date | Mar 26, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory array structure includes a first word line connected to a single port memory cell and a dual port memory cell. The memory array structure also includes a second word line connected to the dual port memory cell. The second word line can control the data storage of the dual port memory during the second phase of a clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.