Reduced line select decoder for a memory array
US6252819A · kind A · utility
2Cited by
10References
6Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 1, 2000 |
| Grant date | Jun 26, 2001 |
| Priority date | — |
| Expiry date | May 1, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A reduced line select decoder for a memory array provided comprising a plurality of memory cells arranged at least in one column, a bit line pair connected to the memory cells arranged in one column, a sense amplifier coupled to a bit line pair for differentially amplifying the voltages on the bit line pair in accordance with the voltage on the sense drive line, and a sense amplifier control input responsive to activation of a sense instructing signal to latch data into the sense amplifier and a pair of read/write control signals to select and provide a read/write operation to a selected bit line and connecting to write buffer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.