Method and apparatus for bridging a plurality of buses and handling of an exception event to provide bus isolation
US6253250A · kind A · utility
86Cited by
6References
32Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 28, 1999 |
| Grant date | Jun 26, 2001 |
| Priority date | — |
| Expiry date | Jun 28, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A bus bridge coupled between two bridges providing bus exception event isolation and address/data translation. In one embodiment the bus bridge includes two direct memory access (DMA) engines and a first-in-first-out (FIFO) buffer interface between the DMA engines to provide the bus exception isolation. The DMA engines and FIFOs also enable a packet based message passing architecture, which eliminates the need for address translation and also handles data reordering.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.