Method and apparatus for double operand load
US6253312A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 7, 1998 |
| Grant date | Jun 26, 2001 |
| Priority date | — |
| Expiry date | Aug 7, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3867
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus and method are provided for concurrently loading single-precision operands into registers in a microprocessor floating point register file. The apparatus includes translation logic, data logic, and write back logic. The translation logic receives a load macro instruction prescribing an address, and decodes the load macro instruction into a double load micro instruction. The double load micro instruction directs the microprocessor to retrieve the two single-precision operands from the address and to load the two single-precision operands into the two floating point registers. The data logic, coupled to the translation logic, executes the double load micro instruction and retrieves the two single-precision operands from the address. The write back logic, coupled to the data logic, loads the two single-precision operands into the two floating point registers during a single write cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.