Three bus server architecture with a legacy PCI bus and mirrored I/O PCI buses
US6253334A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 1, 1997 |
| Grant date | Jun 26, 2001 |
| Priority date | — |
| Expiry date | Oct 1, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L67/10015
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A fault-tolerant computer system includes a processor and a memory, connected to a system bus. The system includes at least two mirrored circuits, at least two mirrored IO devices, a detection means and a re-route means. The two mirrored circuits each include an interface to the system bus, and an IO interface. The input/output interface of each of the mirrored circuits is connected to one of the two mirrored IO devices. Detection means detect a load imbalance in the data transfer between the system bus and either one of the two mirrored IO devices. In response to the detection of a load imbalance, the re-route means re-routes the data transfer between the system bus and the other one of the two mirrored IO devices. In another embodiment, a fault-tolerant computer system includes a first, second and third IO bus, legacy devices, and two IO devices. The first IO bus is connected to the system bus. The legacy devices are connected to the first IO bus. The second and third IO buses are each connected to the system bus. The IO devices are each connected to a corresponding one of the second and third IO buses. An other embodiment of the invention can be characterized as an apparatus for…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.