Dry development process for a bi-layer resist system utilized to reduce microloading
US6255022A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 17, 1999 |
| Grant date | Jul 3, 2001 |
| Priority date | — |
| Expiry date | Jun 17, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG03F7/36
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A new method of forming a bi-layer photoresist mask with a reduced critical dimension bias between isolated and dense lines and reduced edge roughness is described. A layer to be etched is provided on a semiconductor substrate wherein the surface of the layer has an uneven topography. The layer to be etched is coated with a first planarized photoresist layer which is baked. The first photoresist layer is coated with a second silicon-containing photoresist layer which is baked. Portions of the second photoresist layer not covered by a mask are exposed to actinic light. The exposed portions of the second photoresist layer are developed away. Then, portions of the first photoresist layer not covered by the second photoresist layer remaining are developed away in a dry development step wherein sufficient SO.sub.2 gas is included in the developing recipe to reduce microloading to form a bi-layer photoresist mask comprising the first and second photoresist layers remaining. Thereafter, the bi-layer photoresist mask is ashed to smooth its sidewall edges. This completes formation of a bi-layer photoresist mask having a reduced critical dimension bias between isolated and dense lines and re…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.