TFT CMOS logic circuit having source/drain electrodes of differing spacing from the gate electrode for decreasing wiring capacitance and power consumption

US6255695A · kind A · utility

Assignees

• Semiconductor Energy Laboratory Co., Ltd. · JP
• SHARP KABUSHIKI KAISHA · JP

Inventors

• Yasushi Kubota · Sakurai, JP
• Kenichi Katoh · Hiroshima, JP
• Jun Koyama · Yokohama, JP

Key dates

• Filing date: Sep 18, 1997
• Grant date: Jul 3, 2001
• Expiry date: Sep 18, 2017

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D86/421

Abstract

In a field-effect transistor, one of the distance between a gate electrode and a source electrode and the distance between the gate electrode and a drain electrode which one distance is on a side where a signal of a high frequency is applied is made longer than the other distance on a side where a signal of a low frequency is applied.