Method and apparatus for improving capture and lock characteristics of phase lock loops
US6255871A · kind A · utility
0Cited by
2References
14Claims
0Family size
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Key dates
| Filing date | Jan 10, 2000 |
| Grant date | Jul 3, 2001 |
| Priority date | — |
| Expiry date | Jan 10, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/093
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A phase lock loop with an improved capture and lock characteristics. A first displacement error signal, a quadrature error signal, and a second displacement error signal arc generated, the second displacement error signal combining the benefits of the first displacement error signal and the quadrature error signal to more closely approximate an ideal error signal and avoid false lock.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.