Digital programmable delay element
US6255879A · kind A · utility
15Cited by
2References
8Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 1, 2000 |
| Grant date | Jul 3, 2001 |
| Priority date | — |
| Expiry date | May 1, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00058
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The invention is to provide a programmable delay element that can produce a variable delay with many different delay combinations. The invention creates a variable delay through logic gates. A plurality of transmission gates are used to transfer a signal through a plurality of fixed delay lines. Four parallel coupled signal paths, each path having a fixed delay, form the basis of the invention. By selecting a path or by serially adding successive paths, the desired delay of the signal present on the delay line can be achieved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.