Uniform clock timing circuit
US6255884A · kind A · utility
13Cited by
2References
5Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 16, 2000 |
| Grant date | Jul 3, 2001 |
| Priority date | — |
| Expiry date | Feb 16, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A plurality of intermediate driving devices are included in stages between a clock generator and a bank of synchronous logic devices. The outputs of the intermediate devices in each stage are connected in parallel over a wide linear dimension. The timing delay of each circuit is then subject to a small variation depending on the irregularities associated with the device characteristics used in its construction. The outputs of the intermediate devices in each stage are tied together to restore regularity and uniformity to all clock generation circuit outputs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.