Jitter correction circuit and a flat panel display device using the same
US6256003A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 14, 1998 |
| Grant date | Jul 3, 2001 |
| Priority date | — |
| Expiry date | Jan 14, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N5/126
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A jitter correction circuit includes a delayed signal generator and an output circuit. A correction subject signal Ckd0 is derived from multiplying a horizontal synchronization signal or a reference signal Vref. The correction subject signal includes jitters. The delayed signal generator is provided with a plurality of delay elements Fd1 through Fdn which receive and delay the correction subject signal, respectively, by predetermined delay time to generate delayed signals Ckd1 through Ckdn. The output circuit outputs one of the correction subject signal Ckd0 and the delayed signals Ckd1 trough Ckdn on the condition that it has predetermined timing relationship with the reference signal Vref.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.