Ferroelectric memory with shunted isolated nodes
US6256220A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 9, 2000 |
| Grant date | Jul 3, 2001 |
| Priority date | — |
| Expiry date | Mar 9, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A ferroelectric memory includes memory cells comprising a transistor having a source/drain, a ferroelectric capacitor having a first electrode and a second electrode. A plate line is connected to each of the second electrodes. In each memory cell, the first electrode is connected to the source/drain of the transistor to create a node that is isolated when the transistor is off. A shunt system directly electrically connects the isolated nodes of a pair of memory cells at a predetermined time to essentially equalize the voltages on the nodes. The shunt may be a Schottky diode, a resistor, and a pair of back-to-back diodes, or a transistor. In the embodiment in which the shunt is a transistor, the shunt line connected to the shunt transistor gate is boosted, there is a shunt transistor connecting each isolated node in a portion of the memory to the adjacent isolated node, and every eight to thirty-two isolated nodes, another shunt transistor connects the chain of isolated nodes to the plate line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.