Synchronous semiconductor memory device having input buffers and latch circuits
US6256260A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 12, 2000 |
| Grant date | Jul 3, 2001 |
| Priority date | — |
| Expiry date | May 12, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4093
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A synchronous semiconductor memory device having a plurality of external signal input buffer and a plurality of latch circuits, includes: a clock buffer for receiving an external clock signal to generate a buffered clock signal; a chip select buffer for receiving an external chip select signal and the buffered clock signal from said clock buffer to generate a buffered chip select signal, an inverted buffered chip select signal and a latch control signal, wherein the latch control signal is activated when the external clock signal is at the rising edge and the external chip select signal is low; a plurality of external signal buffers for receiving external signals to generate buffered signals and inverted buffered signals; and a plurality of latch circuits for latching and outputting the buffered signals and the inverted buffer signals to an internal logic circuit in response to the latch control signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.