Pixel block compression apparatus in an image processing system
US6256347A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 12, 1997 |
| Grant date | Jul 3, 2001 |
| Priority date | — |
| Expiry date | Aug 12, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N19/61
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A memory efficient image processor receives DPCM prediction error values from decompressed MPEG coded digital video signals in the form of pixel blocks containing luminance and chrominance data in a 4:2:2 or 4:2:0 format and recompresses the pixel blocks to a predetermined resolution. Luminance and chrominance data are processed with different compression laws during recompression. Luminance data are recompressed to an average of six bits per pixel, and only a reference pixel and one other pixel are processed separately from all other luminance pixels in a block. Chrominance data are recompressed to an average of four bits per pixel. Each pixel block is stored with overhead information facilitating efficient and accurate reconstruction. Accurate pixel reconstruction is facilitated by processing a reference pixel accurately; scaling the pixel block; employing quantization tables which are symmetrical and fitted to the domain of the pixel block; biasing negative prediction error values to positive values; using short codewords in quantization tables at levels which are most likely to occur statistically; and processing each pixel with three, four or five bit quantization to ensure ma…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.