Auxiliary buffer for direct map cache
US6256708A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 28, 1997 |
| Grant date | Jul 3, 2001 |
| Priority date | — |
| Expiry date | Aug 28, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0888
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The invention provides a second level cache memory system of the direct map type which moderates possible drawbacks arising from a limitation to such second level cache memory system to realize high speed processing while suppressing the cost as far as possible. The second level cache memory system includes a first level cache memory built in a CPU, and a second level cache memory of the direct map write back type for storing part of addresses and data of a main memory. The second level cache memory allows read/write operations at a higher speed than that for the main memory. A system controller is connected to the main memory for controlling the main memory and the second level cache memory, and includes a second cacheable address, status and data buffer for storing, corresponding to a particular region of the main memory which a user uses frequently or wants to use for processing at a speed as high as possible, a plurality of sets each including an address and data driven out from the second level cache memory by replacement of the second level cache memory and a status parameter of the address in the second level cache memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.