Bus optimization with read/write coherence including ordering responsive to collisions
US6256713A · kind A · utility
78Cited by
4References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 29, 1999 |
| Grant date | Jul 3, 2001 |
| Priority date | — |
| Expiry date | Apr 29, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0831
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides a method and apparatus for optimizing bus utilization while maintaining read and write coherence. More specifically the invention provides bus utilization optimization by prioritizing read transactions before write transactions, where there is no collision pending. When a collision pending is determined, then the read and write transactions are processed according to the age of the transaction(s) allowing for data coherency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.