Digital signal processor with efficiently connectable hardware co-processor
US6256724A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 4, 1999 |
| Grant date | Jul 3, 2001 |
| Priority date | — |
| Expiry date | Feb 4, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3897
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processing system includes a digital signal processor core and a co-processor. The co-processor has a local memory within the address space of the said digital signal processor core. The co-processor responds commands from the digital signal processor core. A direct memory access circuit autonomously transfers data to and from the local memory of the co-processor. Co-processor commands are stored in a command FIFO memory mapped to a predetermined memory address. Control commands includes a receive data synchronism command stalling the co-processor until completion of a memory transfer into the local memory. A send data synchronism command causes the co-processor to signal the direct memory access circuit to trigger memory transfer out of the local memory. An interrupt command causes the co-processor to interrupt the digital signal processor core.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.