Interpreter with reduced memory access and improved jump-through-register handling
US6256784A · kind A · utility
21Cited by
6References
15Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 14, 1998 |
| Grant date | Jul 3, 2001 |
| Priority date | — |
| Expiry date | Aug 14, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/45508
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides an interpreter with reduced memory access and improved jump-through-register handling. In one embodiment, a method includes storing a handler for a bytecode in a cell of a predetermined size of a table, and generating an address of the handler for the bytecode using a shift and an ADD operation. In particular, the handler address is generated by adding a base address of the table and an offset into the table. In another embodiment, a method includes prefetching a target handler address for providing improved jump-through-register handling.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.