Method for manufacturing semiconductor device
US6256875A · kind A · utility
29Cited by
6References
8Claims
0Family size
Assignees
Inventors
Key dates
| Filing date | Sep 22, 1999 |
| Grant date | Jul 10, 2001 |
| Priority date | — |
| Expiry date | Sep 22, 2019 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49165
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The minimum spacing between wires disposed on a printed circuit board of a printed circuit board ball grid array package is reduced. Wiring layers are narrower than in the prior art because they are not plated and because only one metal layer is plated on the wiring layers. The narrower wiring layers can be formed easily with small spaces between wires.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.