Non-volatile semiconductor memory device and method for manufacturing the same

US6258665A · kind A · utility

Assignee

• Kabushiki Kaisha Toshiba · JP

Inventors

• Kazuhiro Shimizu · Yokohama, JP
• Seiichi Aritome · Boise, US
• Kazuhito Narita · Kawasaki, JP

Key dates

• Filing date: Mar 21, 2000
• Grant date: Jul 10, 2001
• Expiry date: Mar 21, 2020

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B41/30

Abstract

The non-volatile semiconductor memory device is formed on a silicon substrate and comprises a plurality of semiconductor active regions defined by a plurality of element isolation regions, a source region and a drain region formed in each of the semiconductor active regions, a charge storage layer which capacitively couples to the semiconductor active region between the source region and the drain region, and a control gate which capacitively couples to the charge storage layer through a second gate insulation film, wherein the second gate insulation film is left extending from the upper surface portion of the element isolation region which lies under the control gate to the upper surface portion of the element isolation region other than the upper surface portion of the element isolation region lying under the control gate.