Voltage stress testable embedded dual capacitor structure and process for its testing
US6259268A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 2, 1999 |
| Grant date | Jul 10, 2001 |
| Priority date | — |
| Expiry date | Apr 2, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/275
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A voltage stress testable embedded dual capacitor structure for use in an integrated circuit (IC). The voltage stress testable embedded dual capacitor structure includes a semiconductor substrate with an electrically insulating base layer thereon, a first embedded dual capacitor and a second embedded dual capacitor connected in series and disposed on the electrically insulating base layer, and a probe pad. The probe pad is electrically connected directly to the first and second embedded dual capacitors at a location therebetween (e.g. by being connected to an electrically conductive top plate of the second embedded dual capacitor). The voltage stress testable embedded dual capacitor structure can be voltage stress tested using an applied voltage high enough to assure the reliability of the first and second embedded dual capacitors, without exposing other electronic devices in the IC to a damaging level of voltage. Also provided is a process for voltage stress testing embedded dual capacitors. The process includes steps of first providing the voltage stress testable embedded dual capacitor structure described above, followed by voltage stress testing the first embedded dual capacito…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.