Method and apparatus for a power-on-reset system
US6259286A · kind A · utility
12Cited by
2References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 15, 1999 |
| Grant date | Jul 10, 2001 |
| Priority date | — |
| Expiry date | Oct 15, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2217/0036
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for a power-on reset system is provided. The power-on reset system comprises a voltage sense circuit for determining whether a voltage level is above a threshold and a write/rewrite verifier circuit for determining whether the voltage level is high enough to write to and rewrite a memory cell content. A power-on reset pulse emitted by the power-on reset system if the voltage level is above the threshold and high enough to write to and rewrite the memory cell. For one embodiment, this is system generates an initial POR pulse upon power-up but can thereafter be selectively disabled and consume zero power.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.