Variable phase shifting clock generator
US6259295A · kind A · utility
21Cited by
11References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 28, 1999 |
| Grant date | Jul 10, 2001 |
| Priority date | — |
| Expiry date | Jun 28, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0812
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method and apparatus is disclosed for generating, based upon user input, clock signals which are delayed by sub-delays which are of a size that is smaller than the smallest achievable delay of a conventional delay element. A user can selectively add one or more sub-delays by providing control inputs which define the desired number of sub-delays to be added.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.