Repairable thin film transistor matrix substrate having overlapping regions between auxiliary capacitance electrodes and drain bus
US6259494A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 22, 1998 |
| Grant date | Jul 10, 2001 |
| Priority date | — |
| Expiry date | Jan 22, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG02F1/136272
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A repairable integrated thin film transistor matrix substrate includes an insulated substrate, and a plurality of parallel gate bus lines and a plurality of accumulated capacitance bus lines formed on the insulated substrate. Each of the accumulated capacitance bus lines extend parallel to and between a pair of the gate bus lines, and has a plurality of auxiliary capacitance electrodes which extend from it. A first insulated film is provided on the gate and accumulated capacitance bus lines and the auxiliary capacitance electrodes. A plurality of operating films are formed on the first insulated film, and on each of the operating films, a corresponding thin film transistors are provided. At least two of the thin film transistors are electrically connected to each of the gate bus lines. Also included is a plurality of parallel drain bus lines which are provided substantially perpendicular to the gate and the accumulated capacitance bus lines on the first insulated film. Each drain bus line electrically connects at least two of the thin film transistors. In addition, a second insulated film having an opening over each of the thin film transistors is provided on the thin film transist…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.