Memory devices with verifying input/output buffer circuits and methods of operation thereof
US6259628A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 18, 1998 |
| Grant date | Jul 10, 2001 |
| Priority date | — |
| Expiry date | Dec 18, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3459
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The disclosure is a nonvolatile semiconductor memory having a plurality of memory cells, the memory cells being programmed and erased. The memory comprises a memory cell array having the memory cells arranged in a matrix, a sense amplifier for detecting a state of the memory cell, an input/output buffer for receiving an output of the sense amplifier and for generating an output responding to the output of the sense amplifier, a verifying circuit for generating an output responding to the output of the input/output buffer, and a control logic block for receiving signals relevant to verifying operations after programming and erasing and for generating signals controlling the input/output buffer and verifying circuit. The verifying operations for programmed and erased cells are conductive through the sense amplifier, the input/output buffer and verifying circuit, in common.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.