Single event upset (SEU) hardened static random access memory cell
US6259643A · kind A · utility
Assignees
Inventor
Key dates
| Filing date | Aug 30, 2000 |
| Grant date | Jul 10, 2001 |
| Priority date | — |
| Expiry date | Aug 30, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4125
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A single event effect hardening technique for removing glitches in digital logic circuits is disclosed. The noise immune latch circuit includes a first input, a second input, and an output. The noise immune latch circuit includes a first set of two cross-coupled transistors, a second set of two cross-coupled transistors, a first set of isolation transistors, and a second set of isolation transistors. The cross-coupling is accomplished by connecting a gate of each transistor to a drain of another transistor in a same set. The first and second sets of isolation transistors are respectively connected to the first and second sets of cross-coupled transistors such that two inversion paths are formed including the two sets of cross-coupled transistors and the two sets of isolation transistors. The noise immune latch circuit changes from one state to another state only upon having incoming input signals of identical polarity being applied contemporaneously at both the first input and the second input. In addition, a delay element is connected between the incoming signals and the second input. The delay element provides a signal delay time equal to or greater than a pulse width of a noise …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.