Signal processing circuit
US6259694A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 27, 1998 |
| Grant date | Jul 10, 2001 |
| Priority date | — |
| Expiry date | Mar 27, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L69/28
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A signal processing circuit which enables an error bit to be set simply without causing an increase in the size of the circuit even if the packet size is changed and which enables realization of stable operation without the system stopping even if the value of the time stamp is impossible. A pre-reception processing circuit decides if a received packet is normally continuous or discontinuous from data in the DBC region of the CIP header. When deciding it is discontinuous, it sets an error bit ERM allocated to one bit of the upper significant 7 bits of the source packet header to "1", and writes this in an FIFO. A post-reception processing circuit, when reading from the FIFO, outputs the data stored in the FIFO to the application side when the error bit ERM is "0" and resets the error bit and outputs a dummy error packet when the error bit EMR is "1".
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.