System architecture for and method of processing packets and/or cells in a common switch
US6259699A · kind A · utility
318Cited by
3References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 30, 1997 |
| Grant date | Jul 10, 2001 |
| Priority date | — |
| Expiry date | Dec 30, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2012/5681
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A novel networking architecture and technique for transmitting both cells and packets or frames across a common switch fabric, effected, at least in part, by utilizing a common set of algorithms for the forwarding engine (the ingress side) and a common set of algorithms for the QoS management (the egress part) that are provided for each I/O module to process packet/cell information without impacting the correct operation of ATM switching and without transforming packets into cells for transfer across the switch fabric.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.