Method and apparatus for mapping bits to an information burst
US6259744A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 30, 2000 |
| Grant date | Jul 10, 2001 |
| Priority date | — |
| Expiry date | May 30, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2001/0098
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A first group of bits (100, 102, 106), e.g., header symbols/bits, are interleaved to form a first group of interleaved bits. A second group of bits (104), e.g., data symbols/bits, are interleaved to form a second group of interleaved bits. The first and second groups of interleaved bits are mapped to an information burst (114). The first and second groups of interleaved bits may be mapped to the information burst relative to a group of known symbols (116) forming a training sequence. A disadvantaged bit location, i.e., a bit location within the mapping having a relative high probability of incurring a bit error, is identified and an advantaged bit location, i.e., a bit location within the mapping having a relatively low probability of incurring a bit error, is identified. A first group bit from the first group of interleaved bits mapped to the disadvantaged bit location is remapped to the advantaged bit location while a second group bit from the second group of interleaved bits mapped to the advantaged bit location is remapped to the disadvantaged bit location.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.