Circuit arrangement and method incorporating data buffer with priority-based data storage
US6260090A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 3, 1999 |
| Grant date | Jul 10, 2001 |
| Priority date | — |
| Expiry date | Mar 3, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processing system, circuit arrangement, integrated circuit device, program product, and method utilize a data buffer with a priority-based data storage capability to handle incoming data from a plurality of available data sources. With such a capability, different relative priority levels are assigned to data associated with different data sources. Such priority levels are then used by control logic coupled to the buffer to control whether or not incoming data is stored (or optionally discarded) in the buffer. In particular, the relative priority of incoming data is compared with that associated with data currently stored in the buffer, with the incoming data being stored in the buffer only when its relative priority exceeds that of the currently-stored data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.