Method and apparatus providing programmable decode modes for secondary PCI bus interfaces
US6260094A · kind A · utility
19Cited by
8References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 13, 1998 |
| Grant date | Jul 10, 2001 |
| Priority date | — |
| Expiry date | Aug 13, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4027
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A PCI-to-PCI having programmable decode modes comprising at least one of a standard bridge data transfer transaction, an intelligent bridge data transfer transaction, and a private address space data transfer transaction, and wherein the transactions are configured to bypass a host bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.