Cache or TLB using a working and auxiliary memory with valid/invalid data field, status field, settable restricted access and a data entry counter
US6260130A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Nov 8, 1996 |
| Grant date | Jul 10, 2001 |
| Priority date | — |
| Expiry date | Nov 8, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/1027
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The memory device includes an auxiliary memory and a useful memory. Both memories are provided with a plurality of memory entries. The auxiliary memory is intended for storing regions of an address space therein. This includes a plurality of addresses with which the useful memory may be addressed. A write/read access to a useful memory entry is not possible if a status field associated with the useful memory entry signals a restricting status and the address with which the useful memory entry is addressed lies within at least one of the address space regions stored in the auxiliary memory. Efficient region-selective flushing of the useful memory is possible with this procedure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.