Automatic configuration of gate array cells using a standard cell function library
US6260177A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 15, 1998 |
| Grant date | Jul 10, 2001 |
| Priority date | — |
| Expiry date | May 15, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system to use a standard cell function library to automatically configure gate array cells in an integrated circuit layout is provided. A standard cell netlist at the transistor level is compiled to list the transistors required in implementing the desired functions. Based on the netlist, gate array cells are restructured so that they can be inserted in locations designed for standard cells. The restructured gate array cells, which are made up of single poly and double poly structures, are strategically placed in a layout. Using the function net connectivity patterns from the standard cell function library, the gate array cells are connected to implement desired logic functions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.