Integrated circuit and the design method thereof
US6260181A · kind A · utility
8Cited by
10References
18Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 27, 1998 |
| Grant date | Jul 10, 2001 |
| Priority date | — |
| Expiry date | Oct 27, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
With this invention, the clock skew of logical integrated circuits is suppressed. To do this, with this invention, chip integrated circuit forming areas are divided into rectangular blocks with the same dimensions, clock drivers are placed in each block, and these clock drivers are connected with basic logic circuits and dummy loads. The total basic logic circuit count and dummy load count is made the same for all clock drivers. This allows the load of each clock driver to be made the same, so generation of clock skew can be suppressed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.