Method and structure for detecting open vias in high density interconnect substrates
US6262579A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 13, 1998 |
| Grant date | Jul 17, 2001 |
| Priority date | — |
| Expiry date | Nov 13, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2203/162
- WIPO fieldMachine tools
- WIPO sectorMechanical engineering
Abstract
A method for testing for open circuits on a common circuit base having pads for making electrical contact to the common circuit base on both the top and bottom of the circuit base. The common circuit base includes a thin film metal interconnect structure formed on its upper surface and the thin film interconnect structure including an upper dielectric layer deposited over a thin film metalization layer that has contact openings etched through the dielectric layer at selected locations for the formation of contact pads. The method includes the steps of (1) forming a seed layer over the upper dielectric layer and over the contact openings; (2) forming a photoresist layer over the seed layer and patterning the photoresist layer to expose selected portions of the seed layer such that the selected portions correspond generally to the contact openings; (3) plating a conductive layer over the patterned seed layer to form plated contact pads that are electrically connected to an underlying thin film metalization layer; and (4) inspecting the plated conductive layer for open circuits prior to performing subsequent process steps and/or tests. In different embodiments, such subsequent process…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.