Output buffer circuit
US6262607A · kind A · utility
Assignees
Inventor
Key dates
| Filing date | Nov 15, 1999 |
| Grant date | Jul 17, 2001 |
| Priority date | — |
| Expiry date | Nov 15, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/00361
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An output buffer circuit has a CMOS output circuit constituted by a p-channel MOS transistor and an n-channel MOS transistor. A combination circuit is provided between an input terminal of the output buffer circuit and the CMOS output circuit. This combination circuit temporarily decreases a signal output to a gate input terminal of the CMOS output circuit when the signal rises from a relatively low first potential level ("L" level) to a relatively high second potential level ("H" level) and temporarily raises the signal when the signal falls from the relatively high second potential level to the relatively low first potential level. Therefore, overshoot, undershoot, and ringing of an output signal can be prevented.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.