Delay locked loop with immunity to missing clock edges
US6262608A · kind A · utility
12Cited by
11References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 15, 2000 |
| Grant date | Jul 17, 2001 |
| Priority date | — |
| Expiry date | May 15, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L2207/14
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method for determining whether to trigger a reset of a delay locked loop ("DLL") comprising calculating the difference in time between a reference clock and a delay clock; comparing the difference in time to the amount of time required for a reset signal to reset said DLL; and generating the reset signal to reset the DLL if the reset time is less than the difference in time between the reference clock and the delayed clock.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.