High-speed data receiving circuit and method
US6262611A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 23, 2000 |
| Grant date | Jul 17, 2001 |
| Priority date | — |
| Expiry date | Jun 23, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0337
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A high-speed data receiving circuit allowing correct and reliable data reception without the need for adjusting delays in circuits and interconnections is disclosed. A sampling circuit samples received data according to first, second, and third clock signals to produce first, second, and third streams of data. The first, second, and third clock signals sequentially have a predetermined phase difference between adjacent ones. A clock generator generates the first, second, and third clock signals having phases determined depending on a clock selection signal obtained by comparing the first, second, and third streams of data. The second clock signal is selected as an output clock signal and the second stream of data corresponding to said second clock signal is selected as an output data of the high-speed data receiving circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.