High efficiency power amplifier having reduced output matching networks for use in portable devices
US6262629A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 6, 1999 |
| Grant date | Jul 17, 2001 |
| Priority date | — |
| Expiry date | Jul 6, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2200/198
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A power amplifier includes a carrier amplifier path and a peaking amplifier path. The carrier amplifier path includes a carrier amplifier (208), and an impedance transforming network (214). The peaking amplifier path includes a peaking amplifier (210), an impedance transforming network (216), and a phase delay quarter wave element (226). The arrangement forms an inverted Doherty combiner where as the nominal impedance at a summing node (230) increases with increased conduction from the peaking amplifier, the load impedance at the output of the carrier amplifier decreases so as to maintain the carrier amplifier at a saturation point as the input signal (232) increases, and results in a reduction of the number of phase delay elements needed over a conventional Doherty approach. In a preferred embodiment the carrier and peaking amplifiers consist of cascaded stages, and are disposed on a common integrated circuit die (304). The impedance transforming networks and phase delay element are disposed on a common substrate (306), as is an input splitter network (308).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.