Silicon power bipolar junction transistor with an integrated linearizer
US6262631A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 25, 1999 |
| Grant date | Jul 17, 2001 |
| Priority date | — |
| Expiry date | Mar 25, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F1/3276
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A power transistor with an integrated linearizer is provided in a package having only standard transistor terminals. The linearizer arranged between the base and collector of the transistor uses a Schottky diode as a nonlinear device that compensates for gain and phase deviations of the transistor. A collector voltage source that supplies power to the transistor provides bias to the diode. A DC blocking capacitor isolates an RF path between the input and output of the transistor from a diode biasing circuit to allow the collector voltage source to provide bias to the linearizer and the transistor separately. A tuning inductor is coupled in series with the DC blocking capacitor to offset the undesired phase rotation introduced by the capacitor. A DC biasing resistor is coupled between the diode and the collector of the transistor to set bias current supplied to the diode and isolate the collector voltage source from the RF path and ground.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.