Semiconductor memory device having a ferroelectric memory capacitor
US6262910A · kind A · utility
14Cited by
7References
27Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 13, 1999 |
| Grant date | Jul 17, 2001 |
| Priority date | — |
| Expiry date | Oct 13, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A switching transistor is provided which applies predetermined voltage to a plurality of word lines based on a predetermined signal from a power on reset circuit, until predetermined potential becomes stable, when the predetermined potential is applied to the bit line or to the plate line, such as at the time of power on, to connect the bit line connected to each memory cell and the memory cell capacitor, as well as applies a control signal to the gate to thereby electrically connect the bit line and the plate line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.