Nonvolatile semiconductor memory device
US6262926A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 1, 2000 |
| Grant date | Jul 17, 2001 |
| Priority date | — |
| Expiry date | Sep 1, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/006
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A nonvolatile semiconductor memory device has a defective block detecting circuit 10 for detecting and temporarily storing a block including a defective memory cell, by detecting the potentials of a memory cell array 1, a row decoder 2, a column decoder 4, a sense amplifier circuit 3, a driving voltage generating circuit 9 for generating a driving voltage boosted in accordance with writing and erasing of data, and a signal line driven by the driving voltage generated by the driving voltage generating circuit 9. The defective block detecting circuit 10 is activated at the beginning of a test control sequence when a batch writing test is carried out every a batch erasing or writing operation every an erasing unit of the memory cell array 1, and a control circuit 7 controls the stop of the supply of the driving voltage to the defective memory cell in the test sequence on the basis of the detected output of the defective block detecting output 10. Thus, even if the defective memory cell is not replaced with a redundant cell array, a batch writing/erasing test can be carried out.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.