Circuit and technique for digital reduction of jitter transfer
US6263034A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 25, 1998 |
| Grant date | Jul 17, 2001 |
| Priority date | — |
| Expiry date | Mar 25, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0338
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A fully digital filter jitter reduction circuit for attenuating jitter transfer in a digital communication system or subsystem includes a digital filter which attenuates jitter transfer within a bandwidth of the filter. A single synthesized clock, from which all other required clocks are created by precessing or phase shifting with respect to the synthesized clock, is utilized to create a reduced jitter output clock. Under the control of the digital filter, the reduced jitter output clock operates an output data latch such that the output data latch performs the function of an elastic buffer. Several stages of the digital filter jitter reduction circuit can be implemented in cascade to further reduce jitter. Since jitter attenuation is a function of the input jitter amplitude, the digital filter is nonlinear in nature.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.