System and method for serial interrupt scanning
US6263395A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 6, 1999 |
| Grant date | Jul 17, 2001 |
| Priority date | — |
| Expiry date | Jan 6, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An interrupt controller may serially scan a plurality of interrupt request signals and/or receive interrupt request signals on parallel inputs. A scan latency may be associated with updating the status of serially scanned interrupt requests. Spurious interrupts may result from the scan latency. To reduce the chance of spurious interrupts, serially scanned interrupt requests may be masked for an amount of time following an end of interrupt (EOI). Write cycles to clear interrupt requests may be posted in a write buffer. The delay of such write cycles clearing the write buffer may also result in spurious interrupts. To reduce the chance of such spurious interrupts, EOI cycles may be delayed or retried until the write buffer empties.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.