Apparatus and method for asynchronous dual port FIFO
US6263410A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 15, 1998 |
| Grant date | Jul 17, 2001 |
| Priority date | — |
| Expiry date | Sep 15, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2205/126
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus and method for controlling an asynchronous dual port FIFO memory is provided. The asynchronous FIFO may operate at frequencies satisfying 0.5f.sub.2 <f.sub.1 <f.sub.2 or 0.5f.sub.1 <f.sub.2 <f.sub.1, where f.sub.2 is the write frequency if f.sub.1 is the read frequency, or vice versa. A FIFO in accordance with the present invention comprises a dual port random access memory, a read pointer, a write pointer, a synchronization circuit and a status indicator. In the FIFO design, the read pointer indicating the read address is a simple sequential counter, and the write pointer indicating the write address is a Gray code counter. Gray code to sequential count converters are used to convert the Gray codes to sequential counts. The synchronization circuit synchronizes the write pointer and the read pointer using a read clock. A status indicator with simple circuits is provided to indicate if the FIFO is almost full or empty.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.