Execution of data dependent arithmetic instructions in multi-pipeline processors
US6263424A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 3, 1998 |
| Grant date | Jul 17, 2001 |
| Priority date | — |
| Expiry date | Aug 3, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30094
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A single chip microprocessor has at least two parallel pipelines that each have multiple processing stages, one of which is an instruction execution stage with a full functioned arithmetic logic unit (ALU). The ALU of one pipeline includes an adder that has the usual two input ports while the adder of the ALU of the other pipeline has at least one extra input port. Two successive arithmetically data dependent instructions are executed by the larger adder alone, while the smaller adder is used as part of a logic circuit that determines the carry bit for the instruction execution result obtained from the larger adder. The smaller adder is thus efficiently used, in an operation where it would otherwise be idle. The additional logic circuitry necessary to determine the carry bit is thus minimized. This additional logic circuitry uses carry bit outputs of both adders, plus the number of adder inputs where the data is inverted in order to execute the instructions, to determine the ultimate carry bit of the instruction execution data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.