Contention based logic gate driving a latch and driven by pulsed clock
US6265897A · kind A · utility
7Cited by
8References
24Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 17, 1999 |
| Grant date | Jul 24, 2001 |
| Priority date | — |
| Expiry date | Dec 17, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0963
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A pseudo-NMOS logic gate of an integrated circuit chip is enabled for a time interval that is substantially less than one-half a clock cycle of the integrated circuit. A latch responds to an output signal of the pseudo-NMOS logic gate for a period that is simultaneous with or slightly less than the time while the pseudo-NMOS logic gate is enabled. The latch derives an output signal commensurate with the output signal of the pseudo-NMOS logic gate while the pseudo-NMOS logic gate is enabled, until the next clock cycle occurs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.