Method and apparatus for switching low voltage CMOS switches in high voltage digital to analog converters
US6266001A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 5, 1999 |
| Grant date | Jul 24, 2001 |
| Priority date | — |
| Expiry date | May 5, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/785
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A varying power supply range, that can exceed the breakdown voltage of switches within a DAC, is used to generate positive and negative generated OFF voltages substantially fixed and less than the breakdown voltage to accommodate a wide range of analog reference voltages and power supply voltages. The digital input signal having digital input levels is received by a TTL/CMOS input receiver and level shifted to logic levels having the positive and negative generate voltage levels. A circuit matches switch resistance and forms positive and negative switch ON voltage levels from the voltage levels of the input positive and negative analog reference levels. Switch drivers properly drive control terminals of the switches with appropriate voltage levels avoiding switch breakdown in response to the digital input signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.