Method and system for optimizing of peripheral component interconnect PCI bus transfers
US6266723A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 29, 1999 |
| Grant date | Jul 24, 2001 |
| Priority date | — |
| Expiry date | Mar 29, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/423
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for optimizing bus transactions in a data processing system is provided. A bus transaction optimizer receives an original bus transaction request which includes an original start address of a target memory for the original bus transaction, an original byte size for a number of bytes for the original bus transaction, and an original bus command for the original bus transaction. The bus transaction optimizer generates multiple bus transaction requests in response to a determination that the original byte size is greater than or equal to a predetermined multiple transfer byte size data value. The multiple bus transaction requests may include at least one high-performance bus transaction request and at least one low-performance bus transaction request. If the original start address is not aligned on a cacheline boundary, the multiple bus transaction requests include a low-performance bus transaction request with an optimized start address equal to the original start address and a high-performance bus transaction request with an optimized start address equal to a cacheline boundary succeeding the original start address. If the original start address is aligned on a cacheline bo…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.