Priority encoding for FIFO memory devices that interface multiple ports to a data receiving device
US6266748A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 30, 1999 |
| Grant date | Jul 24, 2001 |
| Priority date | — |
| Expiry date | Mar 30, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F5/065
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A priority encoding interface transmits data to the receiving device from a highest priority FIFO memory block that is selected from at least two of a plurality of FIFO memory blocks until the highest priority FIFO memory block is empty. The interface inhibits transfer of data to the data receiving device from remaining ones of the FIFO memory blocks, until the highest priority FIFO memory block is empty. Transmission of data from the highest priority FIFO memory block and inhibited transfer of data from remaining ones of the FIFO memory blocks, take place in response to an indication from the data receiving device that the data receiving device is enabled to receive data from the at least two of the FIFO memory blocks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.